Configurable controllers for PCIe 4.0 and CCIX supporting Dual Mode applications
Analog Front End: 4 channels of 12-bit 2 GSPS ADC IQ Pairs, 4 channels of 12-bit 2 GSPS DAC IQ Pairs, PVT & Integrated PLL
The ADC and DAC architecture is optimized to maximize performance while minimizing power and area consumption.
To maximize SNR, the AFE includes an ultra-low-jitter clock distribution network.
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Analog & Mixed Signal IP
- 7-bit, 64 GSPS ADC Ultra Low Power
- USB2.0 Host Transceiver PHY
- Analog Front End: 16x 12-bit 200 MSPS ADCs, 14x Voltage DACs, 4x 250 MSPS DACs, 4x TVM, LDO
- Analog Front End: 2x 12-bit 4 GSPS IQ ADCs, 2x 12-bit 8GSPS IQ DACs, bandgap, temp sensor, PLL, 4 x LDO
- Fibre-Channel Transceiver
- PCI Express PHY serial link PIPE Transceiver IP cell/hard macro