Analog Front End: 8x 12-bit 2 GSPSADCs, 4x 12-bit 200 MSPS ADCs, TVM, PLL, LDO
The AFE includes eight 12-bit, 2GSPS ADCs, four 12-bit 200MSPS ADCs, two TV monitors, multiple LDOs for ADC supplies, and a low jitter fractional-N PLL.
The ADC architecture is optimized to maximize performance while minimizing power and area consumption.
To maximize SNR, the AFE includes an ultra-low-jitter clock distribution network.
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