The CoreAPBLSRAM provides access to the embedded large SRAM blocks present on SmartFusion2 family devices through APB slave interface. It will facilitate convenient access to Fabric SRAM by APB masters. Read and write transactions on the APB are converted into corresponding transfers on the LSRAM and uSRAM.
- Provides configurable memory size that can be configured: - From 512 bytes to 35328 bytes, in steps of 512 bytes for LSRAMs for 32-bit data width - From 64 bytes to 2304 bytes, in steps of 64 bytes for uSRAMs for 32-bit data width
- Provides user configurable parameter to access either LSRAM or uSRAM
- Enables to logically merge multiple SRAM blocks to form large SRAMs or uSRAMs
- APB3 interface with configurable data width of 8, 16, 24, or 32 bits
- Provides support to BUSY output signal from the RAM macros to provide access to the system IP interface (SII) interface