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APB Slave
APB : The Advanced Peripheral Bus (APB) is used for connecting low bandwidth peripherals. It is a simple non-pipelined protocol that can be used to communicate (read or write) from a bridge/master to a number of slaves through the shared bus. The reads and writes share the same set of signals and no burst data transfers are supported. The latest spec is available on ARM website and is a relatively easy protocol to learn.
WASIELA uses APB to interface the MAC layer master to WASIELA’s PHY slave designs.
WASIELA uses APB to interface the MAC layer master to WASIELA’s PHY slave designs.
Features
- APB Salve.
- Configurable and customizable.
- Synthesized on ASIC 40nm TSMC and Xilinx FPGA.
- Compatible with AMBA standard.
Benefits
- Ease of integrating peripherals into large SOCs.
Deliverables
- Synthesizable Verilog.
- System model (Matlab).
- Verilog test bench.
- Comprehensive documentation.
Applications
- APB Master.
- AXI Bus.
- SOC Designs.
View APB Slave full description to...
- see the entire APB Slave datasheet
- get in contact with APB Slave Supplier
APB
- MIPI I3C Controllers - Dual Role Master (70016); APB I3C Slave (70002), Generic I3C Slave
- FlexNoC Network on Chip SoC Interconnect IP
- FlexNoC Resilience Package IP
- Timing Closure Package
- Quad SPI Controller with Execute in Place AHB/APB/AXI
- High Performance Second Generation Extended MIPI CSI2 Receiver