English
You are here:
APB SPI (Serial Peripheral Interface) master and slave
The eSi-SPI core is a Serial Peripheral Interface that can be used to implement full-duplex, synchronous, serial communications between ICs. The eSi-SPI core can operate as a SPI master or slave. Multiple chip-selects are supported in master mode, to allow connection to multiple slave devices. The SPI is supplied with an AMBA APB slave interface and so can be driven by software or via DMA.
Features
- Master or slave operation.
- Programmable word size (1 to 32 bits).
- Programmable bit ordering (MSB first / LSB first).
- Programmable clock polarity (CPOL) and phase (CHPA).
- Programmable bit rate.
- Automatic and manual chip-select generation.
- Multiple chip-select outputs.
- Configurable TX and RX FIFO.
- Configurable support for parallel as well as serial transfers.
- Supports multi-master and multi-slave operation.
- Auto TX and RX to reduce bus bandwidth requirements.
- AMBA 3 APB slave interface.
- DMA flow-control interface.
Deliverables
- Verilog RTL
- Testbench
- Simulation and synthesis scripts
- Documentation
- C API
Block Diagram of the APB SPI (Serial Peripheral Interface) master and slave
View APB SPI (Serial Peripheral Interface) master and slave full description to...
- see the entire APB SPI (Serial Peripheral Interface) master and slave datasheet
- get in contact with APB SPI (Serial Peripheral Interface) master and slave Supplier
SPI
- Octal SPI Flash Controller and PHY
- Quad SPI Controller with Execute in Place AHB/APB/AXI
- AHB Octal SPI Controller with Execute in Place (70114)
- Flash SPI controller master/slave
- Quad-SPI FLASH Controller AHB
- AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA