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180nm FTP Non Volatile Memory for Standard CMOS Logic Process
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APIC - Advanced Programmable Interrupt Controller
The Controller IP for Advanced Programmable Interrupt (APIC) supports up to 32 interrupt sources, including a single Fast IRQ-style interrupt. The Controller IP is architected to quickly and easily integrate into any SoC that supports an ARM® AMBA® 2 Advanced Peripheral Bus (APB). The Controller is compliant with the ARM AMBA 2 specification and is designed to optimize interrupt handling performance by reducing latency, and providing prioritized nesting of interrupts. The Controller is designed to solve interrupt routing efficiency issues in modern multiprocessor computer system applications.
Features
- Programmable edge triggered (rising, falling) or sensitive (high, low) trigger source
- Selectable source for fast IRQ
- Eight levels of hardware priority
- Compliant with ARM AMBA 2 Specification
- Configurable number of interrupt sources
- Supports up to 31 pending interrupt while servicing a single interrupt
- Selectable hardware or software interrupt source
Benefits
- Low-risk solution - silicon-proven design
- Fully configurable - programmable source type, masking
- Easy integration - supports industry-standard APB interface
Deliverables
- Clean, readable, synthesizable Verilog HDL
- Cadence Encounter® RTL Compiler synthesis scripts
- Documentation - integration and user guide, release notes
- Sample verification testbench
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