The Controller IP for Advanced Programmable Interrupt (APIC) supports up to 32 interrupt sources, including a single Fast IRQ-style interrupt. The Controller IP is architected to quickly and easily integrate into any SoC that supports an ARM® AMBA® 2 Advanced Peripheral Bus (APB). The Controller is compliant with the ARM AMBA 2 specification and is designed to optimize interrupt handling performance by reducing latency, and providing prioritized nesting of interrupts. The Controller is designed to solve interrupt routing efficiency issues in modern multiprocessor computer system applications.