ARC Fast FPU: IEEE-754 compliant half-, single- and double-precision scalar and SIMD floating point unit for ARC HS5x, HS5xD, and HS6x Processors
The ARC HS66 and HS68 processors are based on the advanced ARCv3 instruction set architecture (ISA) and pipeline, which provides leadership power efficiency and code density. The processors feature a 52-bit physical address space and can directly address memories up to 4.5 Petabytes (4.5x1015) in size. For applications requiring higher performance, Multicore Processor (MP) versions of the HS66 and HS68 are available with support for up to 12 HS CPU cores and up to 16 hardware accelerators in the processor cluster.
The ARC HS66 features level 1 (L1) instruction and data cache and close coupled memory (CCM) and is optimized for use in high-performance real-time embedded applications. The HS68 is designed for use in applications running Linux or SMP Linux. The HS68 has all the features of the HS66 plus support for L2 cache up to 16 MB and a Memory Management Unit (MMU).
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MMU IP
- ARC HS68MP: Multicore version of ARCv3 ISA based dual-issue HS68 processor with MMU for embedded Linux applications
- Memory management unit (MMU) option for ARC HS5x and HS6x Processor IP
- ARC HS68 64-bit, dual-issue processor with MMU for embedded Linux applications
- MPU incorporating a high performance instruction/data L1 cache controller and Memory Management Unit (MMU)
- 32-bit Basic Application Processor
- 32-bit Application Processor