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Arc hs66 64 bit dual issue processor core interconnect arcv3 isa for embedded applications IP Listing

16 IP Cores

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InCore Calcite Series: 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.

InCore Calcite is a 32/64 Bit RISC-V in-order, single-issue 5-stage pipelined micro-processor. Built on Incore's proprietary deep-customization stack for microarchitectural exploration, Calcite ...

1
Ultra High Performance 64-bit RISC-V Embedded Processor

The S7 Series offers a 64-bit embedded processor targeting high-performance, real-time applications that require 64-bit memory addressability. The S7 core has a superscalar 8-stage in-order ...

2
32-bit Embedded RISC-V Functional Safety Processor

The EMSA5-FS is a processor core designed for functional safety. The fault-tolerant processor uses dual or triple instances of the EMSA5, an efficient 32-bit embedded processor IP core implementing ...

1 Testimonial
Hugh O’Keeffe, CEO, Ashling

3
Optimized for GHz+ operating speeds with minimum area and power consumption, ARC HS Processors are ideal for very high-performance embedded applications

The latest additions to the Synopsys ARC® ARC HS family, the 32-bit ARC HS5x and 64-bit HS6x processors, are based on the new ARCv3 instruction set architecture (ISA). The previous generation ...

4
64-Bit 8-stage superscalar processor that supports RISC-V specification, including GCN

The 64-bit NX45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, and “N” ...

5
64-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux

The 64-bit AX45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” ...

6
Ultra-Low-Power Deeply Embedded RISC-V Processor

The BA51 is a highly configurable, low-power deeply embedded RISC-V processor IP core. It implements a single-issue, in-order, 2-stage execution pipeline, supporting the RISC-V 32-bit base integer ...

1 Testimonial
Hugh O’Keeffe, CEO, Ashling

7
64-bit RISC-V high-performance embedded core

64-bit RISC-V high-performance embedded core. Ideal for control/compute/acceleration workloads requiring high performance and 64-bit capabilities.

8
Low-Power Deeply Embedded RISC-V Processor

The BA53 is a configurable, low-power, deeply-embedded RISC-V processor IP core. It implements a single-issue, in-order, 5-stage execution pipeline, and supports the RISC-V 32-bit base integer ...

1 Testimonial
Hugh O’Keeffe, CEO, Ashling

9
High performance dual-issue, out-of-order, 7-stage Vector processor (DSP) IP

World's first audio DSP IP with RISC-V Vector processor architecture RiVAI-V1 is a dual-issue, Out-of-Order execution, 7-stage pipeline, 32-bit RISC-V processor core that supports the RV32IMFAC ...

10
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCN

The 32-bit N45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, and “N” ...

11
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP)

The 32-bit D45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” ...

12
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux

The 32-bit A45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” ...

13
Certified USB 5G & 10G Dual Mode Controller

The USB 3.0 Dual Mode controller is a highly configurable core and implements the USB 3.0 Host functionality or USB3 Device functionality selectable via a register or an external pin. The host/device ...

14
Display Controller - LCD / OLED Panels (AXI Bus)

The Digital Blocks DB9000AXI LCD / OLED Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI Protocol Interconnect to a LCD or OLED display panel. ...

15
Display Controller - LCD / OLED Panels (AXI4 Bus)

The Digital Blocks DB9000AXI4 LCD / OLED Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI4 Protocol Interconnect to a LCD or OLED display panel. ...

16

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