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Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
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ARINC664 Switch IP Core
ARINC664 Switch IP implements ARINC664 part 7 and provides switching functionality within the ARINC664 network. As an implementation of ARINC664 Switch, IP switches/routes messages of different sizes and different time constraints to their destination with a predictable delay. Two level of priority can be applied to the VLs during configuration of the device. Thus, switch can arrange the data queues according to these priorities. Thanks to the AXI4 interface provided with IP Core, error statistics can be fetched to a desired logic and data injection to the network can be accomplished if desired.
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Block Diagram of the ARINC664 Switch IP Core IP Core
ARINC664 IP
- Multi Protocol Switch IP Core for Safe and Secure Ethernet Network
- Multi Protocol IO Concentrator (RDC) IP Core for Safe and Secure Ethernet Network
- Multi Protocol Switch IP Core for Safe and Secure Ethernet Network
- Multi Protocol Endpoint IP Core for Safe and Secure Ethernet Network
- ARINC664 End System IP Core