The Cortex-A7 processor provides up to 20% more single thread performance than the Cortex-A5 and incorporates all features of the high-performance Cortex-A15 and Cortex-A17 processors, including virtualization support in hardware, Large Physical Address Extensions (LPAE), NEON, and 128-bit AMBA 4 AXI bus interface.
- In-order 8 stage pipeline - Improved dual issue, branch prediction and memory system performance. It features 64-bit load-store path, 128-bit AMBA 4 AXI buses and increased TLB size (256 entry).
- Integrated, Configurable Size Level 2 Cache Controller - Provides low-latency and high-bandwidth access to up to 1MB of cached memory in high-frequency designs, or designs needing to reduce the power consumption associated with off-chip memory access. The L2 cache is optional on Cortex-A7.
- Support Armv7-A extensions - Hardware Virtualization and Large Physical Address Extensions (LPAE) enables the processor to access up to 1TB of memory.
- big.LITTLE technology - First LITTLE processor architecturally compatible with compatible with Cortex-A15 and Cortex-A17 for various big.LITTLE processor combinations.
- Armv7-A architectural extensions (40-bit physical addressing, hardware virtualization support).
- More than 20% improvement in single thread integer performance when compared to Cortex-A5.
- Integrated L2 cache subsystem provides improved area efficiency and up to 43% improvements in memory streaming performance.
- Proven successful design, suited to the needs of wearable mobile devices and other UI-based consumer products.
- Single board computers (SBCs)
- Wired and wireless networking
- IoT - rich nodes
- Network infrastructure
Block Diagram of the Arm Cortex-A7 IP Core