Universal Chiplet Interconnect Express (UCIe 1.0) Controller
Arm Cortex-M0+
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Block Diagram of the Arm Cortex-M0+ IP Core
Arm IP
- 32-Bit RISC-V Embedded Processor and Subsystem. Maps ARM M-0 to M-4. Optimal PPA.
- LC3 / LC3plus Bluetooth LE Audio Codecs for Arm Cortex M55
- LC3 / LC3plus Bluetooth LE Audio Codecs for Arm Cortex M4 & M33
- ARM HSSTP PHY with Link Layer
- SPI Master / Slave Controller w/FIFO (APB Bus)
- eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)