32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
ASIC IP-core for high-throughput decoding of DVB-S2/S2X, and DVB-RCS/RCS2
DVB-S2/S2X LDPC decoder
or as
Six independent DVB-RCS/RCS2 Turbo decoders
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