Attack resistant ECC hardware acceleration core

Features

• Supports any EC over GF(p) of the simplified Weierstrass form that is commonly defined in ECC standards such as NIST, SEC2, Brainpool;
• Supported arithmetic operations: EC Scalar Multiplication (ECSM), EC Addition (ECA), EC Doubling (ECD), Modular Addition (MA), Modular Subtraction (MS), Modular Multiplication (MM), Modular Division (MD), Modular Inversion (MI).
• Supports any key size up to the maximum specified in the pre-synthesis stage;
• Resistant against both Simple and Statistical Timing side channel Attacks (STA), and Simple Power Analysis (SPA) attacks. Optional support for resistance against Differential Power Analysis (DPA) and Doubling Attacks (DA);
• Selection between a ‘small’ and ‘medium’ gate count architectures depending on the processing latency requirements of the application;
• No RAM/ROM blocks used;
• APB interface for loading curve parameters and private key, and unloading the ECSM result.

Benefits

• Easy integration into eSi-RISC or other microprocessor SoC
• Small size and high performance

Deliverables

• RTL
• Testbench
• Software libraries

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