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Audio I2S-TDM Transceiver
signals. It supports master and slave configurations, dynamic routing of multiple channels over a configurable
number of pins, and several sample sizes and frame formats. The Control and Status Registers (CSR) interface
supports the AMBA APB or AXI Lite protocols. The audio data may be input and output via the control interface,
or using the streaming data input and output. The I2 S/TDM Audio Transceiver has four clock domains: the
system clock, the audio master clock, and the receiver and transmitter bit clocks. The bit clocks are used as
true clocks and not as sampled clocks to support a high channel count. The IP is currently supported for use
in ASICs and FPGAs.
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I2S IP
- ASRC-Pro : 24-bit -130dB THD+N Multi-Channel Audio Sample Rate Converter
- I2S/TDM Serial Audio Interface with Asynchronous Sample Rate Conversion
- I2S/Left-Justified/TDM Digital Audio Interface
- ASRC-Lite : 16-bit -90dB THD+N Multi-Channel Audio Sample Rate Converter
- I2S/TDM Multichannel Audio Transceiver
- I2S Receiver/Transmitter