Aurora 64B/66B IP Core
The ALSE Aurora 64B/66B IP core is a very compact and optimized implementation of this protocol, also developed and verified to ensure full compatibility with the Xilinx core (interoperability has been tested and demonstrated).
This IP targets mainly Intel FPGAs but is available for other vendors, and potentially for ASIC projects.
Compared to the 8B/10B version of the Aurora protocol, the 64B/66B flavor addresses the highest lanes speeds (when 8B/10B typically stops around 6 GBs per lane).
It also offers an effective bandwidth of up to 97%, instead of 80% for 8B/10B.
Our IP therefore provides an efficient way to interconnect Intel and Xilinx FPGAs, or any other chip(ASIC, ASSP, etc …) using the Aurora 64B/66B protocol.
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Block Diagram of the Aurora 64B/66B IP Core IP Core
Interface and Interconnect IP
- Standard Compliant AMBA AXI SoC Interconnect, Soft IP
- Standard Compliant AMBA AHB SoC Interconnect, Soft IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Serial Peripheral Interconnect Master & Slave Interface Controller
- Physical Layer Interface Core
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect