The 14Gbps Aurora-like IP Core is based on ALTERA FPGA and enables interoperability between XILINX and ALTERA FPGA.
- Full-Duplex operation.
- Simplex operation.
- Up to 14.1Gbps bit rate per lane (depends on FPGA devices).
- Up to 16 transceiver lanes.
- Framing interface.
- Native flow control in immediate and completion mode.
- User flow control.
- 64b/66b encoding (reduce protocol overhead comparing to 8b/10b)
- Clock compensation sequence generation.
- Per lane polarity inversion.
- Lane skew compensation.
- AXI streaming interfaces.
- REFLEX CES delivers a cost-‐effective solution for each customer project based-‐on an adapted license fee with the following deliveries:
- VHDL source code or encrypted licenses
- User guide
- Reference Designs for ALTERA and XILINX development boards.
Block Diagram of the Aurora-like 64b/66b @14Gbps for ALTERA Devices