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Automotive MIPI A-PHY Sink IP (2-Lane)
The CL12912IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS and autonomous drive subsystems. It supports applications that require long reach (up to 15 meters), error-free links, and high EMI immunity requirement.
PHY IP supports the SINK function of MIPI A-PHY Gear-2 stated in standard specification. It supports data rate up to 4Gbps with integrated mixed signal circuit, high performance RX equalizer, fast tracking Clock and Data Recovery, on chip optional termination resistor calibration.
PHY IP supports the SINK function of MIPI A-PHY Gear-2 stated in standard specification. It supports data rate up to 4Gbps with integrated mixed signal circuit, high performance RX equalizer, fast tracking Clock and Data Recovery, on chip optional termination resistor calibration.
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Block Diagram of the Automotive MIPI A-PHY Sink IP (2-Lane)
MIPI IP
- MIPI CSI-2 Controller Core V2
- MIPI CSI-2 Controller Core
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- I3C Host Controller
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI I3C Controllers - Dual Role Master (70016); APB I3C Slave (70002), Generic I3C Slave