English
You are here:
Automotive MIPI A-PHY Source IP - 1-Lane
The CL12911IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS and autonomous drive subsystems. It supports applications that require long reach (up to 15 meters), error-free links, and high EMI immunity requirement.
PHY IP supports the SOURCE function of MIPI A-PHY Gear-2 stated in standard specification. It supports data rate up to 4Gbps with integrated mixed signal circuit, high performance TX driver, embedded TX clock generation, on chip optional termination resistor calibration.
PHY IP supports the SOURCE function of MIPI A-PHY Gear-2 stated in standard specification. It supports data rate up to 4Gbps with integrated mixed signal circuit, high performance TX driver, embedded TX clock generation, on chip optional termination resistor calibration.
View Automotive MIPI A-PHY Source IP - 1-Lane full description to...
- see the entire Automotive MIPI A-PHY Source IP - 1-Lane datasheet
- get in contact with Automotive MIPI A-PHY Source IP - 1-Lane Supplier
Block Diagram of the Automotive MIPI A-PHY Source IP - 1-Lane
MIPI IP
- MIPI CSI-2 Controller Core
- I3C Host Controller
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI DSI Transmit Controller v1.3
- UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.