The Avalon Multi-port DDR2 Memory Controller IP Core is designed for maximizing the performance of an Altera Nios II processor in Avalon® multi-master streaming data systems. Advanced design features enable maximum system clock rates using low speed FPGA's and standard memory devices, lowering your production cost, and saving you money.
The Avalon Multi-port DDR2 Memory Controller IP Core slave ports can be independently clocked allowing the system to be partitioned and optimized to achieve maximum performance. Supporting post memory read and write cycles, the data FIFO's effectively double memory bandwidth on sequential address or FIFO cache hits. FIFO depth can be tailored for either streaming or random access.
The Avalon Multi-port DDR2 Memory Controller is optimized for Altera® Cyclone, Stratix, and Arria families of field programmable logic devices. The Avalon slave ports are configured with a SOPC Builder Ready component & Qsys GUI which greatly simplifies the design of Avalon-MM based SOC systems.
The SDRAM Memory Controller handles all memory tasks, including initialization and refresh cycles. It is designed to operate asynchronous to the local port clocks enabling the memory to be clocked at its peaked rated frequency maximizing system performance.
- 200 MHz Cyclone / Stratix memory performance
- Supports all standard Mobile DDR SDRAM devices
- 1 to 16 Avalon® independent local bus port interfaces
- Avalon Pipelined and Burst transfers
- Avalon-MM local bus width from 8 to 128-bits
- Altera SOPC Builder Ready & Qsys Configuration GUI simplifies timings
- Integrates seamlessly into Avalon-ST video framework
- Automatic generation of initialization and refresh sequences
- MDDR deep power-down
- Memory data width: 8/16/32/64-bit
- Intelligent SDRAM burst caching controller minimizes wait-states
- Multiple time domain clocking of ports and memory
- IP supports: Cyclone II, III, IV, V, Stratix I, II, II-GX, III, IV/IV GX and Arria GX, II-GX
- Source synchronous MDDR clocking simplifies timing closure
- PCB layout independent DDR Round-Trip capture scheme
- Configurable port FIFO maximizes performance of streaming data applications
- Configurable memory and local bus data width optimizes system cost
- System/memory independent time domain clocking optimizes performance
- Round-robin (default) and user defined bus arbitration schemes
- On Die Termination (ODT) support improves signal integrity
- Altera SOPC Builder Ready & Qsys Configuration GUI
- TimeQuest timing analyzer Synopsis Design Constraint file
- VHDL IP functional simulation models
- Altera OpenCore Plus evaluation license available
- License Options
- Node Locked: Supports a single user. It is tied to the NIC ID of a PC.
- Floating Server: Supports multiple users, typically 1, 2 or 5 seats
Block Diagram of the Avalon Multi-port DDR2 Memory Controller IP Core