The Avalon Multi-port DDR2 Memory Controller IP Core is designed for maximizing the performance of an Altera Nios II processor in Avalon® multi-master streaming data systems. Advanced design features enable maximum system clock rates using low speed FPGA's and standard memory devices, lowering your production cost, and saving you money.
The Avalon Multi-port DDR2 Memory Controller IP Core slave ports can be independently clocked allowing the system to be partitioned and optimized to achieve maximum performance. Supporting post memory read and write cycles, the data FIFO's effectively double memory bandwidth on sequential address or FIFO cache hits. FIFO depth can be tailored for either streaming or random access.
The Avalon Multi-port DDR2 Memory Controller is optimized for Altera® Cyclone, Stratix, and Arria families of field programmable logic devices. The Avalon slave ports are configured with a SOPC Builder Ready component & Qsys GUI which greatly simplifies the design of Avalon-MM based SOC systems.
The SDRAM Memory Controller handles all memory tasks, including initialization and refresh cycles. It is designed to operate asynchronous to the local port clocks enabling the memory to be clocked at its peaked rated frequency maximizing system performance.