The Digital Blocks DB-SPI-FLASH-CTRL is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting access to Single/Dual/Quad SPI Flash Memory devices by way of Boot, Execute-in-Place (XIP), Processor Memory-Mapped IO, or optional DMA.
The DB-SPI-FLASH-CTRL contains an AHB Slave Interconnect allowing for Memory Read of Flash Memory via the SPI Master Bus, and an AHB-Lite, AHB, or APB Slave Interface for Processor Configuration and Memory Read/Write of Flash Memory.
- Master SPI Controller Targeting SPI Flash Memory Access
- SPI Flash Memory:
- Supports CPU access of SPI Flash memory
- Boot, Execute-In-Place (XIP), and DMA (optional features)
- Flash Memory from Adesto, Cypress/Spansion, Macronix, Micron, and Winbond
- Supports SPI Mode0, Mode3 at 166 MHz
- Up to N=8 Slave Select (SS) Outputs supporting multiple SPI Flash Memory devices
- Configurable SPI Modes:
- Standard SPI Mode (1 Data Lane)
- Dual SPI Mode (2 Data lanes)
- Quad SPI Mode (4 Data Lanes)
- Octal SPI Mode (8 Data Lanes)
- Programmable LSB-first or MSB-first Per Word
- Transmit/Receive FIFOs:
- Dual-Clock designs
- User configurable depths
- Two Clock Domains:
- Internal interrupts with masking control
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.