AXI Bridge for PCI Express (PCIe) Gen3 Subsystem
The AXI4 PCIe core provides a transaction level translation of AXI4 commands to PCIe TLP packets and PCIe requests to AXI4 commands.
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Interface and Interconnect IP
- Standard Compliant AMBA AXI SoC Interconnect, Soft IP
- Standard Compliant AMBA AHB SoC Interconnect, Soft IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Serial Peripheral Interconnect Master & Slave Interface Controller
- Physical Layer Interface Core
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect