The AXI PCIe® Gen 3 core provides an interface between the AXI4 interface and the Gen 3 PCI Express (PCIe) silicon hard core. The AXI4 PCIe sub-system provides full bridge functionality between the AXI4 architecture and the PCIe network. The sub-system is composed of the PCIe core, the GT interface and the AXI4 interface. The bridge circuit is implemented in the FPGA fabric and the PCIe core and GT are hard-core elements in the FPGA.
The AXI4 PCIe core provides a transaction level translation of AXI4 commands to PCIe TLP packets and PCIe requests to AXI4 commands.
- Maximum Payload Size (MPS) up to 256 Bytes
- Messaged Signaled Interrupt (MSI)
- Memory mapped AXI4 access to PCIe space
- PCIe access to memory mapped AXI4 space
- Tracks and manages TLP completion processing
- Detects and indicates error conditions with interrupts
- Ingress, Egress Outstanding Transactions (2 to 32)
- Ingress, Egress Address translation (32b to 64b width)
- Supports up to six PCIe 32-bit PCIe Base Address Register (BAR) as Endpoint