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AXI- Interconnect : Advanced Extensible Interface Bus IP
The AMBA AXI protocol is targeted at high-performance, high-frequency system designs and includes a number of features that make it suitable for high-speed submicrons interconnect.
Features
- AMBA AXI Bus Specification version 2.0
- Functions as:
- Master
- Slave
- Interconnect
- Supports all valid burst transfer types
- Supports 2 Masters and 5 Slaves
- Supports any valid topology
- Interconnect is working under the principle of SAMD (Shared Address and Multiple Data )
- Supports optional two levels of address pipelining
- Supports 4KB split bus architecture (simultaneous read and simultaneous write)
- AXI lite Master is working under common ID
- Interconnect has competence knowledge about master and slave in the system
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AXI IP
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- XpressCCIX-AXI Controller IP for PCIe 5.0 with CCIX ESM support
- Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC with AMBA AXI User Interface
- FlexNoC Network on Chip SoC Interconnect IP
- FlexNoC Resilience Package IP
- Timing Closure Package