The AXI Memory Mapped to PCIe® Gen2 IP core provides an interface between the AXI4 interface and the Gen2 PCI Express (PCIe) silicon hard core. The AXI4 PCIe provides full bridge functionality between the AXI4 architecture and the PCIe network. The IP is composed of the PCIe core, the GT interface and the AXI4 interface. The bridge circuit is implemented in the FPGA fabric and the PCIe core and GT are hard-core elements in the FPGA.
The AXI4 PCIe core provides a transaction level translation of AXI4 commands to PCIe TOP packets and the PCIe requests to AXI4 commands.
- Support AXI4 memory access to PCIe memory
- Provide AXI4 master access for PCIe devices
- Translate AXI4 transactions to appropriate PCIe Transaction Layer Packets (TLP) packets
- Track and Manage PCIe TLPs that require completion processing
- Indicate error conditions detected by the PCIe core through interrupt