The AXI Protocol Checker core is designed to monitor AXI interfaces. When attached to an interface, it actively checks for protocol violations and provides an indication of which violation occurred.
The checks are synthesizable versions of the System Verilog protocol assertions provided by ARM in the “AMBA 4 AXI4, AXI4-Lite, and AXI4-Stream Protocol Assertion” library.
- Supports checking for AXI3, AXI4 and AXI4-Lite protocols
- Interface data widths:
- AXI4 and AXI3: 32, 64, 128, 256, 512 or 1024
- AXI4-Lite: 32 or 64 bits
- Address width: Up to 64bits
- USER width (per channel): Up to 1024 bits
- ID width: Up to 32bits
- Programmable messaging levels for simulation operation.
- Supports monitoring of multiple outstanding READ and WRITE transactions
- Supports Exclusive transaction checks
- Instrumented to support Vivado Debug Nets and connections to Vivado logic analyzer monitoring