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65nm OTP Non Volatile Memory for Standard CMOS Logic Process
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AXI Quad SPI
The AXI Quad Serial Peripheral Interface connects the AXI4 interface to those SPI slave devices which are supporting the Dual or Quad SPI protocol along with Standard SPI protocol instruction set. As an example, this core provides a serial interface to SPI slave devices such as SPI serial flash from Winbond/Numonyx which support Dual and Quad SPI protocol along with Standard SPI interface. The Dual/Quad SPI is the enhancement to the Standard SPI protocol that delivers a simple method for a master and a selected slave to exchange data.
Features
- Configurable AXI4 interface; when configured with an AXI4-Lite interface the core is backward compatible with version 1.00 of the core (legacy mode)
- Configurable AXI4 interface for burst mode operation for the Data Receive Register (DRR) and the Data Transmit Register (DTR) FIFO
- Configurable eXecute In Place (XIP) mode of operation
- Connects as a 32-bit slave on either AXI4-Lite or AXI4 interface
- Configurable SPI modes:
- Standard SPI mode
- Dual SPI mode
- Quad SPI mode
- Programmable SPI clock phase and polarity
- Configurable FIFO depth (16 or 256 element deep in Dual/Quad/Standard SPI mode) and fixed FIFO depth of 64 in XIP mode
- Configurable Slave Memories in dual and quad modes are: Mixed, Micron, Winbond, and Spansion (Beta Version)
View AXI Quad SPI full description to...
- see the entire AXI Quad SPI datasheet
- get in contact with AXI Quad SPI Supplier
Interface and Interconnect
- FlexNoC Network on Chip SoC Interconnect IP
- Cache Coherent Interconnect
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- Serial Peripheral Interconnect Master & Slave Interface Controller
- Physical Layer Interface Core