The Xilinx® LogiCORE™ IP AXI SmartConnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.
The AXI SmartConnect is a Hierarchical IP block that is added to a Vivado® IP Integrator block design in the Vivado Design Suite.
AXI SmartConnect is a drop-in replacement for the AXI Interconnect v2 core. AXI SmartConnect is more tightly integrated into the Vivado design environment to automatically configure and adapt to connected AXI master and slave IP with minimal user intervention.
- Up to 16 Slave Interfaces (SI) and up to 16 Master Interfaces (MI) per instance
- Instances of SmartConnect can be cascaded to interconnect a larger number of masters/slaves or for organizing the interconnect topology
- AXI Protocol compliant
- Burst transactions are automatically split, as needed, to remain AXI compliant
- Interface Data Widths (bits):
- AXI4 and AXI3: 32,64,128,256,512 or 1024
- AXI4-Lite: 32 or 64-bit
- Transactions between interfaces of different data widths are automatically converted by AXI SmartConnect