4Kx16 Bits OTP (One-Time Programmable) IP, UMC 110 nm 1.2V/3.3V L110AE Process
AXI Streaming FIFO
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Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP
- PCIe Controller for USB4 Hosts and Devices supporting PCIe Tunneling, with optional built-in DMA and configurable AMBA AXI interface