The AXI Sysmon ADC IP Core is a 32-bit slave peripheral that connects to the AXI4 (Advanced eXtensible Interface) and provides the troller interface for System Monitor (SYSMON) hard macro on Virtex®-6 family of FPGAs. This document describes the specifications for AXI Sysmon ADC IP Core.
- AXI4-Lite interface is based on the AXI4 specification
- Connects as a 32-bit AXI4-Lite slave
- Uses dedicated System Monior (SYSMON) hard macro on Virtex-6 devices
- Supports 10-bit, 200-kSPS (kilo-Samples Per Second) Analog-to-Digital Converter (ADC)
- Supports on-chip monitoring of supply voltages and temperature
- Supports 1 dedicated high bandwidth differential analog-input pair and 16 auxiliary low bandwidth differential analog-input pairs
- Supports automatic alarms based on user defined limits