AXI4-Stream Accelerator Adapter
It provides the AXI4-Stream interface to AXI4 infrastructure components and BRAM/FIFO interface towards Accelerator IP. This IP is used to improve the overall system-level performance for hardware accelerator IP in the FPGA logic.
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Interface and Interconnect IP
- Standard Compliant AMBA AXI SoC Interconnect, Soft IP
- Standard Compliant AMBA AHB SoC Interconnect, Soft IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Serial Peripheral Interconnect Master & Slave Interface Controller
- Physical Layer Interface Core
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect