The AXI4-Stream Accelerator Adapter is a soft Xilinx® LogiCORE™ Intellectual Property (IP) core used as a infrastructure block for connecting hardware accelerators to embedded CPUs.
It provides the AXI4-Stream interface to AXI4 infrastructure components and BRAM/FIFO interface towards Accelerator IP. This IP is used to improve the overall system-level performance for hardware accelerator IP in the FPGA logic.
- Connects as a 32-bit slave on AXI4-Lite interface
- AXI4-Stream data width support of 32, 64, 128, and 256 bits
- BRAM/FIFO data width support of 8, 16, 32, and 64 bits
- Supports up to eight channels for Stream-to-Memory (S2M), Memory-to-Stream (M2S), and Memory-to-Memory (M2M)
- Supports up to four buffers per channel
- Supports asymmetric Multi-Buffer data width for AXI4-Stream and BRAM/FIFO interface
- Supports up to eight input scalars, eight output scalars, and eight input scalars for scalar interface