AXI4-Stream Interconnect
Xilinx provides the AXI4-Stream Interconnect core which provides capability to connect multiple master/slave AMBA® AXI4-Stream protocol compliant endpoint IP.
The AXI4-Stream Interconnect is a key Interconnect Infrastructure IP which enables connection of heterogeneous master/slave AMBA® AXI4-Stream protocol compliant endpoint IP. The AXI4-Stream Interconnect routes connection from one or more AXI4-Stream master channels to one or more AXI4-Stream slave channels.
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Interface and Interconnect IP
- Standard Compliant AMBA AXI SoC Interconnect, Soft IP
- Standard Compliant AMBA AHB SoC Interconnect, Soft IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Serial Peripheral Interconnect Master & Slave Interface Controller
- Physical Layer Interface Core
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect