The S3BGT40L1V8 is a reference circuit which has been designed to provide 1.203V output stable voltage to reduce time to market, risk and cost in the development of Analog Front-Ends and Regulators.
The S3BGT40L1V8 is a standard implementation using an array of matched PNP transistors to generate the PTAT (Proportional to Absolute Temperature) term.
- 40nm TSMC Logic LP Process, 6 Metals Used
- 1.6V – 3.6V Power Supply Voltage
- 1.203V 2.5% Output Voltage
- High PSRR and Low Noise Output
- Current Consumption of 100uA
- Compact Die Area: 0.068mm2
- Power Down Mode
- The S3BGT40L1V8 has been implemented on standard 65nm LP basic logic process. However, it is readily portable to any similar manufacturing process. Any activity of this nature can be fully supported.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- *Subject to Agreement
- Reference Generation
- Current and Voltage Regulation
- General Mixed Signal Products
Block Diagram of the Bandgap Reference IP Core