The JPEG-DX-S IP core is an area-efficient, high-performance JPEG decoder conforming to the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 standard.
It decompresses JPEG images, and also video payload for Motion-JPEG container formats. It supports 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats. The decoder processes one color sample per clock cycle, enabling it to process multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG decoders available, it requires just 76,000 equivalent gates when mapped on an ASIC technology.
Once programmed, the easy-to-use encoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host pro-cessor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed.
SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and decompressed data, and a 32-bit APB slave interface for registers access.
Customers with a short time to market requirements can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG encoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.
The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its delivera-bles include a complete verification environment and a bit-accurate software model.
- Area-efficient, high-performance 8/12-bit JPEG decoder for ASIC and FPGA
- Standards Support
- ISO/IEC 10918-1 Standard Baseline and Extended Decoder (Sequential DCT modes)
- Single-frame JPEG images and Motion JPEG payloads
- Up to four color components>
- 8- and 12-bit color samples
- All widely used color-sub-sampling formats, and any image size up to 64k x 64k
- All scan configurations and all JPEG formats
- All marker segments expect DNL
- Up to four Huffman Tables
- Up to four b-nit or 18-bit Quantization tables
- AXI Streaming I/O data interfaces
- APB Control/Status interface
- Optional AHB wrapper with DMA capabilities
- Performance and Size
- One decoded sample per clock cycle
- Small silicon footprint (~76k Gates)
- Ease of Integration
- Requires no programming or control from host
- Reports image format
- Detects and reports marker syntax errors
- Delivered with bit-accurate software model
- Optional Block-to-Raster Conversion with AXI or standard memory interface towards the lines buffer
- Verilog RTL source code
- Sophisticated self-checking Testbench
- Software (C++) Bit-Accurate Model
- Sample simulation and synthesis scripts
- Comprehensive user documentation
- The JPEG-DX-S core’s excellent performance and low silicon resource usage make it suitable for implementing a variety of digital imaging applications, including:
- Residential, corporate, airborne, and other security or surveillance systems.
- Machine vision and video link decoders/terminals for industrial, defense, or other systems.
- Medical imaging system, and advanced driver assistance systems.
Block Diagram of the Baseline and Extended JPEG Decoder Core