Zero latency, low gate count, low power, asynchronous BCH Code based Error Correction FEC:
The whole operation of encoding and decoding is asynchronous and is pure combinatorial gates without use of any synchronous logic, making it zero latency RTL.
Symbol Size is 1 bit and variables are ‘m’ bits wide for Galois Field operations.
Every symbol and primitive polynomial used of degree ‘m’ and ‘n’ is ((1<<‘m’)-1) .Shortened ‘n_short’ is less than ‘n’ where symbols (‘n’ – ‘n_short’) are 0 . If the code has ‘t’ error correcting capability then ‘k’ = no. of message symbols. The number of ECC bits depends on degree of the generator polynomial, 'l' . So the total number of message bits that can be transferred are k = n - l .
Here n = 2**m - 1 and l is degree of generator polynomial.
RTL is completely configurable for ‘m’ , ‘n_short’ or ‘t’. Typically, but not necessarily ‘m’ lies between 5 to 15
ECC, number of parity symbols is 'l'
Errors_correctable are upto ‘tt’, if more than ‘tt’ errors then indicated as uncorrectable.
The Error correcting Code consists of:
A. It has programmable input data bus width. The whole encoding can be completed in 0 cycle
A. Syndrome Calculator: It can generate all syndromes in 0 clocks, or serially in as large as ‘n_short’ clocks
B. BerlekampMasy Circuit: it generates error locator polynomial for Chien search engine
C. Parallel Chien Search Engine: It finds error locations in as little as 0 clock or as large as ‘n_short’ clocks
Is ideally suitable for RAMs in ASIC / FPGA for fault tolerance It can protect against any errors caused due to manufacturing defects. This could increase the yield as most ASICs are about 40%-70% static rams.
The other applications can be in high speed communication where errors get introduced due to noisy channel.