The BCH Encoder/Decoder is full featured, easy to use into FPGA and SoC designs. To be easily integrated with the system interface, the IP core is delivered with a simple interface based on flow transfer. However, our connection modules can be customized, or new custom bus can be developped to fit as best as possible to customer's need.
The BCH Encoder/Decoder allows to fit as well as possible between your latency contraints and your area constraints with the possibility of customized the Chien Search algorithm, with the possibility of implemented the best Galois Field you need and the data path of your application.
The BCH Encoder/Decoder IP Core is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. It is fully tested with test benches models and hardware tested with FPGAs. The package includes RTL code, technical documentation, and complete test environment.
- possibilities to configure:
- -> Size of the block
- -> number of correctable error bits
- -> data width
- -> parallelisation of the Chien Search algorithm
- Verilog RTL source code.
- Synthesis scripts for Xilinx, Altera and Design Compiler.
- Technical documentation.
- Simulation testbench, with error injection.
- One year of maintenance and technical support.
- Supported simulators
- MTI Modelsim.
- Cadence NC-Verilog.
Block Diagram of the BCH Encoder / Decoder IP Core