Bi-Directional LVDS with LVCMOS
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Block Diagram of the Bi-Directional LVDS with LVCMOS IP Core
LVDS IP
- TSMC 3nm (N3E) 1.5V LVDS
- TSMC 3nm (N3E) 1.2V LVDS Tx/Rx with 1.8V BGR
- MIPI D-PHY/LVDS Combo CSI-2 RX (Receiver) in TSMC 28HPC+
- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
- MIPI DPHY & LVDS Transmit Combo on GF55LPe
- MIPI D-PHY/LVDS Combo TX (Transmitter) for Automotive in Samsung 28FDSOI