The S3PMBIAST90 circuit has been designed to reduce time to market, risk and cost in the development of power management blocks. A range of supporting IP blocks such as Low drop regulators (LDO), Power-on-reset (POR), Analog-to-Digital (ADC) and Digital-to-Analog (DAC) converters are also available.
The S3PMBIAST90 has been implemented on standard 90nm LP basic logic process. However it is readily portable to any similar manufacturing process. Any activity of this nature can be fully supported.
The Bandgap circuit is a standard implementation using an array of matched PNP transistors to generate the PTAT (Proportional To Absolute Temperature) term.
- 90nm TSMC Logic LP Process, 5 Metals Used
- 3.3V and 1.2V Supplies
- Accurate 1.17V Bandgap Reference
- Tolerance of Bandgap Voltage < ±3.5%
- Power consumption
- Active mode:1.09mW
- Power down: 0.5uW
- Compact Die Area:0.054mm2
- The Bandgap voltage is used to create accurate bias currents. These bias currents are generated with an internal and external resistor.
- The S3PMBIAST90 is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioral Model (Verilog)
- Integration Support
- Reference Generation
- Current & Voltage Regulation
- General Mixed Signal Products
Block Diagram of the Bias Block in TSMC 90nm LP