Built-In-Self-Test (BIST) is usually used to make faster, less-expensive manufacturing tests. Logic BIST is extensively used. Although it was once reserved for complex digital chips, it can now be used for mixed- signal IPs.
The ISI-220 is a BIST IP used in testing the USB PHY which is a mixed-signal block. It supports low/full/high speed. This is especially helpful in detecting defects in the analog section of the PHY. It is required that the PHY-under-test supports loop-back.
- The ISI-220 uses a pattern generator implemented with 16-bit linear feedback shift registers (LFSR).
- This type of pattern generator can produce pseudorandom patterns of width n, with 2n-1 unique combinations before repeating (every possible combination except all zeros).
- The pattern is completely deterministic when the initial conditions are known. The ISI-220 configures the USB PHY in the loopback mode. It then transmits the data generated by the pseudo random pattern generator and checks to verify that the received data is the same as the transmit data. This test can be used during debug, characterization or manufacturing.
- Faster less expensive manufacturing test
- Low number of pins required
- Small area overhead
- Less intrusive to the design flow
- RTL Verilog of the ISI-220
- Verilog Test Bench
- Design Manual