Blockchain has a wide range of applications on the internet. As it is decentralized by design, it is an alternative to the many traditional transactional systems. In order for a blockchain system to be viable (scalability, interoperability and sustainability), the complex and time/power consuming cryptographic operations associated with the blockchain should be offloaded to an accelerating system. Our solution is a secure public key infrastructure engine that can be used to offload compute-intensive public key operations such as signature generations and verifications.
The blockchain hardware accelerator uses a combination of a load dispatcher and a configurable number of instances of our Public Key Crypto Engine (BA414EP). This saves time and space as the transaction load is distributed among several components, thereby increasing the overall transaction speed and output. The architecture allows for high performance offloading and supports all the cryptography algorithms such as ECC. ECDSA operations that are used by popular blockchain applications like Ethereum, Ripple and Bitcoin and Hyperledger are supported next to EdDSA using the Edwards25519 curve as used in the Libra blockchain.
Offer 3 Solutions (See block Diagram for more information):
Plug & Play Solution for Xilinx Alveo Cards
The Alveo Cards from Xilinx is proven to be one of the best-in-class for blockchain transactions. When our Blockchain Hardware Accelerator is added, it gives an extremely high performance that can securely process an incredible amount of signature verifications.
Cloud Solution for Amazon Web Service (AWS) F1
Accelerate your transactions even further by adding our Blockchain Hardware Accelerator to the Amazon EC2 F1 instances. Easy to deploy and with tremendous output.
IP Core Solution for FPGA/ASIC Integration
The Blockchain hardware accelerator IP core is easily portable to ASIC and FPGA. It supports a wide range of applications on various technologies. The unique architecture enables a high level of scalability enabling a trade-off between throughput, area and latency.
Please find more information in the block diagram
- Wide variety of ECC curves supported (Weierstrass, Edwards, Montgomery, Twisted-Edwards, …)
- Ideal for FPGA/ASIC integration
- The unique architecture of our solution enables high scalability that in turn provides a trade-off between throughput, area and latency. This flexibility allows for an optimal performance for any application regardless of the platform on which the solution is implemented. It can easily be ported to ASIC and FPGA, and supports a wide range of applications in blockchain scaling, cryptocurrency transactions, cloud computing and data centers. In addition our drivers have an asynchronous API (or non-blocking API) which are integrated in OpenSSL Async.
- Netlist or RTL
- SW drivers (Linux)
- Scripts for synthesis & STA
- Self-checking RTL test-bench based on referenced vectors
- Digital (crypto) currency
- Transaction verification
- Online voting
- Data storage
Block Diagram of the Blockchain Hardware Accelerator IP Core