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Memory BISR (Built in self repair) IP
Memory BISR (Built in self repair) IP families provide both hard repair and soft repair for SRAM and embedded DRAM. We invent a flexible remapping technique to have spare row, spare column, and spare cluster with the same redundancy. The repair algorithm is 1D/2D compatible. We also provide a redundancy analysis service to suggest users the most efficiency repair algorithm, redundancy volume, and test algorithm. This BISR IPs are fully compatible with Brains, which supports IEEE1149/1500 interface.
Features
- Repairing Algorithm
- ESP (Essential Spare Pivoting)
- Row first
- Column first
- Supported External Storage
- eFuse
- OTP
- Testing Algorithm
- All march based algorithm
- MOVI
- Checkerboard background
- Test Interface
- Basic
- Mini-basic
- IEEE 1149.1
- IEEE 1500
Benefits
- Users can detect SRAM's defect and repair its defect by using HEART.
- HEART supports "Hard-repair", "Soft-repair" and our unique "Accmulative-repair" based on requirement of SoCs.
- HEART supports expect SRAM's test and repair during FT stage, users can enable"On-Demand" SRAM testing and repairing circuit by programming MCU/CPU or triggering one signal of HEART based on HEART.
Block Diagram of the Memory BISR (Built in self repair) IP
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BISR
- High Speed Single Port (SP TCAM) Ternary CAM Compiler on TSMC 16FF+ GL
- High Speed Single Port (SP TCAM) Ternary CAM Compiler on TSMC 16FF+ LL
- Ultra High Speed Single Port (SP TCAM) Ternary CAM Compiler on Samsung 14LPP
- High Speed Single Port (SP TCAM) Ternary CAM Compiler on TSMC 28HPM
- Low power, high speed, and high density configurable SRAM
- Low power, high speed, and high density configurable SRAM