Memory BISR (Built in self repair) IP

Memory BISR (Built in self repair) IP families provide both hard repair and soft repair for SRAM and embedded DRAM. We invent a flexible remapping technique to have spare row, spare column, and spare cluster with the same redundancy. The repair algorithm is 1D/2D compatible. We also provide a redundancy analysis service to suggest users the most efficiency repair algorithm, redundancy volume, and test algorithm. This BISR IPs are fully compatible with Brains, which supports IEEE1149/1500 interface.

• see the entire Built-in self-repair (BISR) mechanism datasheet
• get in contact with Built-in self-repair (BISR) mechanism Supplier