The Camera Link Aligner IP Core is designed for building Frame Grabber (Receiver) Medium & Full Channel Link™ interfaces in conjunction with the SerDes blocks of Altera FPGA devices. The core includes supports for the adjunct Camera Link serial control and data communication signals.
The Link Aligner synchronizes the data between Channel Links in Medium and Full Camera Link Frame Grabber configurations. The using FIFO's the ALigner synchronizes the data across Links by removing delays caused by phase differences of the clock sources between Channel Links or cable length mismatches. The Link Aligner block compares the LVAL signal from each Channel Link and using FIFO's auto adjusts the our delays to bring the links into phase alignment. It also synchronizes data at the output Ports to the STROBE/XCLK clock.
The IP also includes a Power Over Camera Link (PoCL) SafePower logic block, which when implemented with supporting hardware, allows a Frame Grabber to provide DC power to PoCL cameras and while still remaining compatible with non-PoCL cameras. The SafePower IP block works with the PoCL circuitry on the Camera Link Receiver HSMC Daughter Card.