The Camera Link® IP Core is a high-speed LVDS transmitter / receiver pair that conforms to the standard Camera Link protocol originally developed by National Semiconductor Corp®. The design is comprised of an independent transmitter and receiver that may be implemented separately or together as a single transceiver unit. The IP Core may be used in either the BASE, MEDIUM or FULL configurations as defined in the Camera Link specification. In general, each data lane can support around 500 Mbps per LVDS lane on basic FPGA and SoC devices. This gives a typical throughput of around 2 Gbps over the 4 data lanes (BASE), 4 Gbps over 8 lanes (MEDIUM) or 6 Gbps over 12 lanes (FULL).