The BitCsi2Rx IP is a receiver for camera sensor signals, to be used in an FPGA or ASIC.
It receives camera signals in accordance with the MIPI CSI-2 and D-PHY specifications. BitCsi2Rx converts these signals to parallel video signals for AXI4- Stream Video standard. To make it easier to interface BitCsi2Rx with various other design blocks, it also outputs fval (frame valid) and lval (line valid) signals for synchronization.
A MIPI CSI-2 transmitter IP is also available from BitSim, BitCsi2Tx.
- 1 to 4 data lanes
- Number of data lanes can be configured statically at synthesis time and dynamically during run-time
- Supported CSI-2 Primary Data Types: like RAW8/10, YUV422_8, RGB888, Generic, User Defined
- Up to 1.2 Gb/lane
- AXI4-Stream Video output with additional synchronization signals
- Virtual Channel Support
- ECC checking and correction for packet headers and short packets
- Checksum checking for packet payload data
- D-PHY protocol decoding included
- Clock-lane/data-lanes deskew
- Full High Speed/Low Power mode support Test/debug features
- Written in VHDL, prepared for instantiation in Verilog or SystemVerilog design
- Encrypted or readable source code
- VHDL test benches and scripts
- HW-platform/reference kit available
- Radar etc
Block Diagram of the Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard