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CAN 2.0 Controller with DMA
The GRCAN core is a CAN controller with an AHB DMA backend. The APB bus is used for configuration, control and status handling and the AHB bus is used for retrieving and storing CAN messages in memory external to the CAN controller. GRCAN supports transmission and reception of sets of messages by use of circular buffers located in memory external to the core. Separate transmit and receive buffers are assumed. Reception and transmission of sets of messages can be ongoing simultaneously.
Features
- 20-1000 kbps bitrate
- CAN 2.0B with standard and extended frame format
- Message filtering
- DMA using circular buffers of configurable size
- Single shot transmission
Deliverables
- Source code
- Synplify project file
- VHDL test bench
- Template design for LEON3 processor
- FPGA evaluation board (optional)
Block Diagram of the CAN 2.0 Controller with DMA IP Core
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