CAN FD Bus Controller

Features

• Implements CAN2.0A and CAN2.0B protocol, ISO 11898-1 compliant
• Supports CAN-FD
• Non-ISO CAN FD – Compliant to Bosch Protocol
• Independent System Clock(SYSCLK) and CAN Bus Clock(CANCLK)
• SYSCLK is CPU interface Bus Clock, – AHB Clock in case of ARM
• CANCLK can either be independent or tied to SYSCLK
• Flexible shared buffering scheme that implements optimal buffer size for Transmit and Receive messages
• Total buffer size is parameterized – synthesis time option
• Buffer can be implemented as a single port SRAM or flops
• Transmit buffer, receiver buffer and high-priority transmit buffer
• CPU configurable depths for transmit, receive and high-priority transmit buffers
• Parameterized number of Acceptance Filters – 1-16
• AHB-Lite Slave Interface for connecting to CPU
• Optional APB Interface
• Supports 32-bit interface
• Programmable Baud Rate Prescalar (BRP)
• Generate Time Quantum Clock from CANCLK
• 8-bit BRP register to have div-by-2 up to div-by-255

Benefits

• CAN2.0A, CAN2.0B and non ISO protocols
• Small footprint
• Code validated with Spyglass
• Functionality ensured with comprehensive verification
• Premier direct support from Arasan IP core designers

Deliverables

• Verilog HDL of the IP Core
• User guide
• Gate count estimates available upon request
• Synthesis scripts
• Simulation environment including test bench, BFM’s, and exhaustive test suite

Applications

• Automotive Networks for ECUs requiring >1Mbps
• Industrial and Medical networks

Block Diagram of the CAN FD Bus Controller IP Core

• see the entire CAN FD Bus Controller datasheet
• get in contact with CAN FD Bus Controller Supplier