4Kx16 Bits OTP (One-Time Programmable) IP, UMC 110 nm 1.2V/3.3V L110AE Process
CAN-SEC Acceleration Engine
Arasan’s CAN-SEC Acceleration Engine core is easy to integrate with the Host processor using AMBA-APB, AHB_Lite or AMBA-AXI standard interface. This highly configurable design supports programmable Interrupts, data and baud rates, acceptance filters & buffering schemes specific to the application.
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Block Diagram of the CAN-SEC Acceleration Engine IP Core
![CAN-SEC Acceleration Engine Block Diagam](http://www.design-reuse.com/sip/blockdiagram/53102/20230810011317-main-CAN-SEC-with-CAN-XL-Controller.png)
Video Demo of the CAN-SEC Acceleration Engine IP Core
Arasan, a leading provider of semiconductor IP for all things mobile, including automobiles released its 2’nd generation of CAN IP FPGA demo video.