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Many-Channel Centralized DMA Controller with AMBA AXI Interconnect
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Capless LDO IP core - TSMC130nm, 20mA
The capless LDO IP core is optimized for high performance fast switching digital applications (e.g. DDR and GDDR). The capless LDO IP core can hold a steady output voltage reference with less than +/- 5% overshoot/undershoot without using an external capacitor. The LDO uses Vidatronic's Noise Quencher (TM) technology to provide unparalled power supply rejection at high frequencies.
Features
- Input Power Supply: 2.5 V to 3.3 V
- Output Voltage: 1.0 to 1.9 V (adjustable)
- Maximum Load Current: 20 mA
- Contact Vendor for Product Brief
Benefits
- Adds value to your microchip with embedded power management
- Fewer components and smaller board area (NO external capacitor)
- Improved reliability
- Reduced inventory and reduced BOM management overhead
- Longer battery life (save power through integration)
- Low risk for customer product/program with a silicon proven capless LDO IP core.
Deliverables
- GDSII
- Spice Netlist and/or Cadence Schematic
- IP Datasheet, User’s Guide, and Test Plan
- Behavioral Model
View Capless LDO voltage regulator (130 nm, 20 mA, excellent load transient) full description to...
- see the entire Capless LDO voltage regulator (130 nm, 20 mA, excellent load transient) datasheet
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Power Management IP
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