China Multimedia Mobile Broadcasting (CMMB) LDPC decoder

Features

• Compliant with CMMB specifications, block size of 9216 bits, code rates 1/2 and 3/4.
• Frame by frame programmability of code rate and number of iterations.
• Syndrome based LDPC iteration stopping and indication.
• ASIC and FPGA proven.
• Throughput of 50Mbps on FPGA platform.
• Low power design.

Benefits

• Silicon proven and FPGA proven

Deliverables

• Verilog source code (optional VHDL) or verilog EDIF netlist.
• Extensive test bench environment.
• C/Matalb bit accurate model.
• Detailed ocumentation.