The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for the Spartan®-6 GTP transceiver is a customizable core that can be used to evaluate and monitor the health of the Spartan-6 GTP transceivers. The design includes pattern generators and checkers implemented in Field Programmable Gate Array (FPGA) logic, as well as access to the ports and dynamic reconfiguration port (Dynamic Reconfiguration Port) DPR attributes of the serial transceivers. Communication logic is also included and allows the design to be run-time accessible through Joint Test Action Group (JTAG). The IBERT core is a self-contained design, and when generated, runs through the entire implementation flow, including bit stream generation.
- Provides a communication path between the ChipScope Pro Analyzer software and the IBERT core
- Has user-selectable number of Spartan-6 GTP Transceivers
- Each transceiver can be customized for the desired line rate, reference clock rate, reference clock source, and data path width
- Requires a system clock that can be sourced from a pin or one of the enabled serial transceivers