The ChipScope™ Pro IBERT core for Virtex®-7 FPGA GTX transceivers is customizable and designed for evaluating and monitoring Virtex-7 FPGA GTX transceivers. This core includes pattern generators and checkers that are implemented in FPGA logic, and access to ports and the dynamic reconfiguration port attributes of the GTX transceivers. Communication logic is also included to allow the design to be run-time accessible through Joint Test Action Group (JTAG). This core can be used as a self-contained or open design, based on customer configuration as described in this document.
- Provides a communication path between the ChipScope Pro Analyzer software and the IBERT core
- Provides a user-selectable number of Virtex-7 FPGA GTX transceivers
- Transceivers can be customized for the desired line rate, reference clock rate, reference clock source,and data path width
- Requires a system clock that can be sourced from a pin or one of the enabled GTX transceivers